library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity registrador_saida is
	port(
		Lo_neg, CLK : in std_logic; -- neg significa negado (risco em cima)
      entrada_bw  : in std_logic_vector(7 downto 0);
     	saida       : out std_logic_vector(7 downto 0):="00000000"
   );
end registrador_saida;

architecture arquitetura of registrador_saida is
begin
	process (CLK,Lo_neg)
   begin
	  	if (CLK'event and CLK='1') then
	      if(Lo_neg='0') then
		      saida<=entrada_bw;
   	   end if;
   	end if;
   end process;
end arquitetura; 
